1. Field of the Invention
An embodiment of the present invention relates to sequential logic elements. In particular, an embodiment of the present invention relates to vectored flip-flops and latches with embedded output-merge logic and shared clock drivers.
2. Background of the Related Art
Integrated circuits are widely used in many applications. One example of an integrated circuit is a microprocessor, which has many applications. Within microprocessors are datapaths called pipestages. These pipestages are datapaths for data signals and can be configured for various logic arrangements. The length of a pipestage dictates the amount of time a data signal takes to travel the datapath and arrive at an output. The shorter the pipestage, the faster a data signal can be processed.
Within the pipestage are various logic stages the data signal must travel through to implement the desired logic arrangement. Two common logic stages are flip-flops and latches. Each logic stage requires a certain amount of time to complete. In conventional designs, the delay (datapath penalty) of going through a flip-flop and/or latch has become too large because of input and output inverters of the driver elements within the pipestage. For example, a ten logic stage design from the passgate output of a latch to the passgate input of the next latch may go through two wasted stages: one output inverter of the driver element, and one input inverter of the receiver element. For a microprocessor with even shorter number of logic stages per pipestage, such as six logic gates/pipestage, two may be wasted, which is a ⅓rd loss of that pipestage.
Another area of concern in conventional microprocessors is the power consumption. For example, in a microprocessor with pushed frequencies, the number of storage elements (flip-flops/latches) can become very large. Thus, the storage elements become a significant contributor to the total power consumption of the microprocessor. A large proportion of total microprocessor power ( greater than xcx9cxe2x88x9230%) comes from load residing within sequential cells, of which more than half is in the local clock drivers and their loads. Often, these clock-drivers tend to underflow (become clamped to lowest allowable size value) because the passgates they drive are small enough already. However, they still consume power.
These and other disadvantages exist in conventional circuitry.